00100	@                         STANFORD UNIVERSITY
00200	                     Stanford, California 94305
00300	
00400	COMPUTER SCIENCE DEPARTMENT                          16 November 1970
00500	
00600	
00700	@3
00800	@4
00900	@5
01000	
01100	ATTENTION:  @1
01200	
01300	
01400	SUBJECT:  Request for Computer Memory Proposals
01500	
01600	
01700	Gentlemen:
01800	
01900	We plan to purchase  two  computer  memory  subsystems  in  the  near
02000	future.    Our  needs  for primary memory are rather well defined and
02100	are  summarized  in  paragraph  1  and  detailed  in   the   enclosed
02200	specification.    We  have  a  requirement  for  cache memory that is
02300	difficult to summarize concisely, but is  outlined  in  paragraph  2.
02400	More  complete  information  about  the  cache  can  best be obtained
02500	through dialogue.
02600	
02700	1.  Primary Memory
02800	
02900	By 19 December 1970 we expect to select a vendor for primary memories
03000	and will place an order as soon as it can be negotiated.  There  must
03100	be at least two independent memory units, each with a capacity of 16K
03200	x 148 bits or equivalent, and up to double that amount if prices  are
03300	favorable.
03400	
03500	These units must have a cycle time of 2 microseconds  or  less.  They
03600	will  be  connected  initially  to  an existing multiprocessor system
03700	(Digital Equipment Corporation PDP-10 and PDP-6).    The enclosed RFP
03800	is  nearly  identical  to  one issued on 5 June 1970, but with timing
03900	specifications relaxed.
04000	
04100	We   are  willing  to  consider  either  buying  memory  modules  and
04200	constructing the interfaces  ourselves,  or  buying  complete  memory
04300	systems that are plug-compatable with the DEC memory busses.  We will
04400	be able to spend up to about $180,000 for memory units,  or  $200,000
04500	for  a  system  complete  with a four-port interface.  Very favorable
04600	consideration will be given to lower-priced proposals.
04700	
04800	2.  Cache Memory
04900	
05000	By 1 February 1971 we expect to order  several  small  memories,  the
05100	largest  of  which  may  be  thought of as containing 256 x 288 bits.
05200	These memories must have an access time of 45 nanoseconds or less and
05300	a cycle time of 100 nanoseconds.  We expect to pay no more than about
05400	50 cents a bit, hopefully much less.
05500	
05600	The cache memory will be incorporated in a new central processor that
05700	we plan to construct.  It will serve as a  pseudo-associative  buffer
05800	between primary memory and the processor.  The fabrication of the new
05900	processor is to be completed by about May of 1971 and it  will  share
06000	the primary memories cited above.
06100		
06200	3.  Actions
06300	
06400	If you have something that appears applicable as cache memory, please
06500	call  as  soon  as  possible  to  Mr.  David  Poole  at 415/321-2300,
06600	extension 4971.   He is more likely to be found in the afternoon  and
06700	evening.
06800	
06900	Proposals to supply primary  memories  should  be  in  duplicate  and
07000	should  reach  me  by  10  December 1970.  If you have any questions,
07100	please call me at 415/321-2300, extension 4202.
07200	
07300	
07400	Very truly yours,
07500	
07600	
07700	
07800	Lester D. Earnest
07900	Executive Officer
08000	Artificial Intelligence Project
08100	
08200	
08300	enclosure: Computer Memory Performance Specification
     

00100	                         STANFORD UNIVERSITY
00200	                     Stanford, California 94305
00300	
00400	ARTIFICIAL INTELLIGENCE PROJECT                      16 November 1970
00500	
00600	
00700	              Computer Memory Performance Specification
00800	
00900	1.  General
01000	
01100	The  memory  described  herein  shall  be used to augment the primary
01200	storage of a PDP-10/PDP-6 computer system at Stanford University  and
01300	shall have the following characteristics:
01400		number of units:  2 or more
01500		unit capacity:  at least 16K x 148 bits, or equivalent
01600		cycle time:  2 microsecond or less
01700		access time:  800 nanoseconds or less
01800	Either  complete  memory  systems  or  subsystems  may  be  proposed.
01900		proposal due date:  10 December 1970
02000		decision due:  19 December 1970
02100		delivery:  6 months or less
02200	
02300	2.  Existing System
02400	
02500	The existing computer system has four independent memory  buses  with
02600	processors connected as follows:
02700		1. high speed data channel (24 million bits/second) to
02800		   Librascope disc file and television cameras,
02900		2. multiplexed channel to III and Data Disc display
03000		   processors and IBM 2314 disk file.
03100		3. PDP-10 processor,
03200		4. PDP-6 processor.
03300	Existing memories include two manufactured by Ampex (1 us, 32K  words
03400	each,  2-way  interleaved)  and  four from DEC (2 us, 16K words each,
03500	4-way interleaved). In the case where  more  than  one  processor  is
03600	requesting  service  from  a  given  memory, priority is given in the
03700	order 1, 2, alternating 3 and 4.  Parity  checking  of  transfers  is
03800	done in each processor.
03900	
04000	3.  Additional Memory
04100	
04200	The memory system specified herein is to be connected to the existing
04300	memory  bus  system.
04400	
04500	    3.1  Memory Units
04600	
04700	The  cycle  time for a read or write cycle of a memory unit shall not
04800	exceed 2 microseconds and each unit shall  be  capable  of  sustained
04900	operation  at this rate.  A somewhat shorter cycle time is desirable.
05000	The  read  access  time  (time  from  availability  of   address   to
05100	availability of data) must not exceed 800 nanoseconds.
05200	
05300	Proposals  to  provide  the  specified capacity by assembling smaller
05400	modules are  quite  acceptable.  A  read-modify-write  capability  is
05500	desirable and, if offered, the minimum cycle time should be specified.
05600	If memories are offered without  interfaces,  the  control  and  data
05700	connections should be described.
05800	
05900	    3.2  Memory Interfaces (optional)
06000	
06100	Memory  interfaces,  if  offered,  must  connect  to the existing DEC
06200	PDP-10 memory buss, It is recommended that firms  planning  to  offer
06300	memory  interfaces  discuss  their  approach  with Stanford technical
06400	personnel before proposing.
06500	
06600	    3.3 Test Equipment
06700	
06800	The Seller shall provide any test equipment necessary for maintenance
06900	and  adjustment  of  the  memory  other  than  a  Tektronix  type 547
07000	oscilloscope with Tektronix type P6020 current  probe  and  type  134
07100	amplifier, and a 20,000 ohms per volt multimeter.
07200	
07300	4.  Construction, Power, and Utilities
07400	
07500	All  equipment  shall be so constructed as to permit accessibility to
07600	any and all component parts for ease of maintenance  and  replacement
07700	-- without disconnecting any external cables.  All construction shall
07800	be of the highest quality according to electronic industry standards.
07900	
08000	If  a  complete memory system is offered, the Seller shall supply all
08100	racks, cabinets, cooling fans, power supplies,  and  other  equipment
08200	required for operation.
08300	
08400	All  terminals,  plugs,  connectors,  circuit  wiring,  etc. shall be
08500	uniquely labeled on the equipment and referenced to a set  of  system
08600	drawings.   Adequate interlocks and safety devices shall be installed
08700	wherever necessary to insure the safety of personnel and equipment.
08800	
08900	The operating line  voltage  for  the  system  shall  be  taken  from
09000	commercially  available  power  at Stanford.  This power is 117V/208V
09100	single phase or 208V/440V  4-wire  Wye-connected  three  phase  at  a
09200	frequency  of  60  Hertz  plus  or  minus  2 Hertz.  The system shall
09300	operate over an input voltage fluctuation of plus  or  minus  10%  of
09400	normal.    Protection  against  damage  from power transients is very
09500	desirable.
09600	
09700	The system shall operate as specified within a room temperature range
09800	of +55 to +100 degrees F.  Any internal cooling requirements shall be
09900	supplied by the Seller.
10000	
10100	5.  Reliability and Acceptance Testing
10200	
10300	The system will normally be in use  on  a  24-hour  day,  7-day  week
10400	basis.   It  should  have a mean time between failure greater than 28
10500	days and an availability of 99%.  (Availability  is  defined  as  the
10600	percentage  of  the  time that the memory is usable, discounting both
10700	scheduled and unscheduled maintenance.)
10800	
10900	Acceptance testing may begin whenever the memory system is  correctly
11000	connected  to  the  computer.   The  test  shall consist of operating
11100	continuously for 28 days with no more than  one  malfunction  in  the
11200	memory system.
11300	
11400	6.  Special Requirements
11500	
11600	If a complete memory system (with interfaces) is procured,  then  the
11700	Seller  shall  install  the  system  at  Stanford  and shall instruct
11800	Stanford maintenance personnel, a maximum  of  six  persons,  in  the
11900	logic, electronics, and mechanics of the entire system.
12000	
12100	The  Seller  shall  supply  four complete sets of instruction manuals
12200	adequate for operation and maintenance of the equipment.  The  Seller
12300	shall  also  supply  four  complete sets of circuit schematics, logic
12400	drawings, and mechanical drawings as are necessary  for  maintenance,
12500	operation, and repair, and wiring diagrams for the entire system.
12600	
12700	The  Seller  shall  supply  a  Recommended  Spare  Parts  List and an
12800	estimate of the cost.
12900	
13000	The Seller shall supply and bear the cost of  all  replacement  parts
13100	prior  to  final  acceptance.   A longer parts warranty is desirable.
13200	Proposals should indicate a period of time during  which  any  parts
13300	that  fail will be replaced at no charge to the Buyer.  At the option
13400	of the Offeror, this feature may be costed separately.
13500	
13600	The Seller shall supply  a  complete  description  of  the  interface
13700	between  the  system and the Buyer's equipment three months after the
13800	date of contract.
13900	
14000	The proposal should contain precise  specifications  of  cycle  time,
14100	access  time,  power  consumption, environmental conditions required,
14200	and delivery time.
     

00100	@
00200		@@	foo@
00300	Mr. Ron Livingston	408/734-4330
00400	Advanced Memory Systems, Inc.
00500	1276 Hammerwood Ave.
00600	Sunneyvale, Calif. 94086
00700	
00800	Marketing Dept.	408/246-0330
00900	American Micro-systems Inc.
01000	3800 Homestead Road
01100	Santa Clara, Calif.  95051
01200	
01300	Mr. B. Trick	415/367-3861
01400	Ampex Corperation
01500	120 Independence Drive
01600	Menlo Park, Calif. 94025
01700	
01800	Marketing Dept.	617/969_0050
01900	Cambridge Memories, Inc.
02000	285 Newtonville Ave.
02100	Newtonville, Mass. 02160
02200	
02300	Marketing Dept.	 
02400	Cogar Corporation
02500	All Angels Road
02600	Wappingers Falls, New York
02700	
02800	Mr. Doug Folder	415/964-4000
02900	Core Memories Inc.
03000	2525 Charleston Road
03100	Mountain View, Calif.  94040
03200	
03300	Mr. Robert C. Tenten	609/924-3331
03400	Dataram Corp.
03500	Route 206
03600	Princeton, New Jersey 08540
03700	
03800	Mr. E. Frost	415/326-5640
03900	Digital Equipment Corporation
04000	560 San Antonio Road
04100	Palo Alto, Calif. 94306
04200	
04300	Mr. Ron Kasper	415/327-3706
04400	Electronic Memories Inc.
04500	701 Welch Road, Suite 310
04600	Palo Alto, Calif. 94304
04700	
04800	Mr. James Coffey	408/739-4780
04900	Fabri-Tek Inc.
05000	363 Taafe Avenue, Suite 220
05100	Sunnyvale, Calif. 94086
05200	
05300	Mr. H. Martin	415/347-7701
05400	Ferroxcube Corp., c/o W. J. Purdy Co.
05500	770 Airport Blvd.
05600	Burlingame, Calif. 94010
05700	
05800	Mr. C. Jamgotchian	408/732-0120
05900	Honeywell, Inc.
06000	910 Thompson Place
06100	Sunnyvale, Calif. 94086
06200	
06300	Mr. David G. Dow	415/328-3200
06400	IBM Corperation
06500	525 University Ave.
06600	Palo Alto, Calif. 94301
06700	
06800	Marketing Dept.	415/961-8080
06900	Intel Corperation
07000	365 Middlefield Road
07100	Mountain View, Calif.  94040
07200	
07300	Mr. R. Douglas Shute	213/641-0770
07400	Lockheed Electronics Co.
07500	6201 East Randolph St.
07600	Los Angeles, Calif. 90022
07700	
07800	Mr. Bruce Kaufman	213/772-4220
07900	Memory Systems Inc.
08000	3341 W. El Segundo Blvd.
08100	Hawthorne, Calif.  90250
08200	
08300	Marketing Dept.
08400	Plessey Company, Ltd.
08500	111A Powder Mill Road
08600	Maynard, Mass.
08700	
08800	Mr. Howard F. Kinkopf	714/546-1055
08900	RCA Memory Products
09000	4500 Campus Drive
09100	Newport Beach, Calif.  92660
09200	
09300	Marketing Dept.	213/988-1570
09400	Signal Galaxies Inc.
09500	6955 Hayvenhurst Ave.
09600	Van Nuys, Calif. 91406
09700	
09800	Mr. Bruce Billington	714/835-5466
09900	Standard Logic, Inc.
10000	1630 S. Lyon St.
10100	Santa Ana, Calif.
10200	
10300	Mr. Jack Devine	213/788-3010
10400	Standard Memories Inc.
10500	15130 Ventura Blvd.
10600	Sherman Oaks, Calif.  91403
10700	
10800	Mr. Y. Kinoshita	213/644-8625
10900	TDK Electronics
11000	931 S. Douglas St.
11100	El Segundo, Calif.  90245
11200	
11300	Marketing Dept.	713/526-1411 nobid
11400	Texas Instruments Inc., Digital Systems Division
11500	P. O. Box 66027
11600	Houston, Texas 77006